Publications
You can also find my articles on my Google Scholar profile.
Book Chapter
- Domain isolation and access control in multi-tenant cloud FPGAs
In Security of FPGA-Accelerated Cloud Computing Environments, Springer International Publishing, 2023
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Patent
- Gray-box Hardware Penetration Testing Framework for Hardware Security Verification
US Patent, filed (under review) , 2025
Journal Papers
- Rethinking System-on-Chip Verification for Secure Cross-layer Interactions
IEEE Design & Test, 2025
[paper] - VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation
arXiv preprint arXiv:2507.13369, 2025
[paper | source code] - SVAgent: AI Agent for Hardware Security Verification Assertion
arXiv preprint arXiv:2507.16203, 2025
[paper] - DeepV: a model-agnostic retrieval-augmented framework for verilog code generation with a high-quality knowledge base
arXiv preprint arXiv:2510.05327, 2025
[paper] - Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy
ACM Transactions on Reconfigurable Technology and Systems (TRETS), 18(2), 1–44, 2025
[paper] - SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
arXiv preprint arXiv:2506.20415, 2025
[paper] - Llm for soc security: A paradigm shift
IEEE Access, 2024
[paper]
Conference Papers
- LAsset: An LLM-assisted Security Asset Identification Framework for SoC Verification
Accepted at Design, Automation, and Test in Europe (DATE) conference, 2026
- GEmFuzz: Uncovering System-Level Vulnerabilities in SoCs via Emulation-Based Grey-Box Fuzzing
Accepted at Asia and South Pacific Design Automation Conference (ASP-DAC), 2026
- Automating Security Monitoring Event Generation for SoCs Using Large Language Models
Accepted at Government Microcircuit Applications and Critical Technology (GOMACTech) Conference, 2026
- Threat2SVA: Threat Model and CWE-Aware Security Assertion Generation Using LLM
Accepted at Government Microcircuit Applications and Critical Technology (GOMACTech) Conference, 2026
- Emulation-based Fuzzing for System-level Vulnerability Detection
Accepted at Government Microcircuit Applications and Critical Technology (GOMACTech) Conference, 2026
- Trusting the Machine: How Secure is LLM-Generated RTL Code?
ACM/IEEE Symposium on Machine Learning for CAD (MLCAD), 2025
[paper | slide] - Enhancing Hardware Security: Detecting Vulnerabilities in HDL Codes Using Fine-Tuned Large Language Model
Annual Government Microcircuit Applications and Critical Technology (GOMACTech) Conference, 2025
- SocureLLM: An LLM-Driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2025
[paper | slide] - BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection
IEEE VLSI Test Symposium (VTS), 2025
[paper] - Cultivating Security: Debug Authentication for Ensuring the Security of SoC's Root of Trust
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2025
[paper | slide] - EmFIA: A Novel Emulation-based Fault Injection Vulnerability Assessment Framework at RTL Level
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2025
[paper | slide] - Continuity in Security: Leveraging LLM for Translating Security Properties Across Hardware Designs
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2024 (Best Paper candidate)
[paper | slide] - Empowering Hardware Security with LLM: The Development of a Vulnerable Hardware Database
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2024
[paper] - Case Study: Fault-Injection Vulnerability Assessment at RTL Level
IEEE Physical Assurance and Inspection of Electronics (PAINE), 2024
[paper | slide] - SAP: Silicon Authentication Platform for System-on-Chip Supply Chain Vulnerabilities
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2024
[paper | slide] - Lasp: LLM Assisted Security Property Generation for SoC Verification
ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), 2024
[paper | slide] - TDM: Time and Distance Metric for Quantifying Information Leakage Vulnerabilities in SoCs
IEEE International Conference on Computer Design (ICCD), 2024
[paper | slide] - OpenTitan Based Multi-Level Security in FPGA System-on-Chips
International Conference on Field Programmable Technology (ICFPT), 2023
[paper | slide] - A Hardware/Software Architecture for System-on-Chip Security
Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), 2023
- Trusted IP Solution in Multi-Tenant Cloud FPGA Platform
IEEE World Forum on Internet of Things (WF-IoT), 2022
[paper] - Metrics for Assessing Security of System-on-Chip
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2022
[paper] - A Security Architecture for Domain Isolation in Multi-Tenant Cloud FPGAs
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021
[paper] - Domain Isolation in FPGA-Accelerated Cloud and Data Center Applications
Great Lakes Symposium on VLSI (GLSVLSI), 2021
[paper | slide] - Performance Study of Multi-Tenant Cloud FPGAs
IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2021
[paper] - System-on-Chip (SoC) Security through Dynamic Policy Enforcement in Hardware Accelerators
Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), 2021
- FPGA Accelerated Embedded System Security through Hardware Isolation
Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2020
[paper] - Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS), 2020
[paper] - STGM: Spatio-Temporal GPU Management for Real-Time Tasks
IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2019
[paper | slide] - A Reconfigurable Layered-Based Bio-Inspired Smart Image Sensor
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019
[paper] - MeXT: A Flow for Multiprocessor Exploration
IEEE High Performance Extreme Computing Conference (HPEC), 2019
[paper | slide] - Synthesis of Hardware Sandboxes for Trojan Mitigation in Systems on Chip
IEEE High Performance Extreme Computing Conference (HPEC), 2019
[paper | slide] - Byte-Based Partial-Match Instruction and Data Compression for High-Performance and Low-Power Interconnects
IEEE International New Circuits and Systems Conference (NEWCAS), 2016
[paper | slide] - A Survey on Interconnect Encoding for Reducing Power Consumption, Delay, and Crosstalk
IEEE International Conference on Electrical Information and Communication Technologies (EICT), 2015
[paper] - Modified Bus Invert Encoding to Reduce Capacitive Crosstalk, Power, and Inductive Noise
IEEE International Conference on Electrical Information and Communication Technologies (EICT), 2015
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